A conventional semiconductor device may use many signals. The signals used in the semiconductor device may be externally applied or internally generated. Additionally, signals may be used in a region of the semiconductor device or distributed and used throughout the semiconductor device.
For example, a clock signal is a signal that may be distributed and used throughout the semiconductor device. The clock signal may be applied to various circuits implemented inside the semiconductor device. The circuits to which the clock signal is applied, may operate in synchronization with the clock signal such that the semiconductor device is operable at a proper rate in response to the clock signal. The semiconductor device or the circuits inside the semiconductor device and the external device may mutually input and output various signals at proper timings. Accordingly, the clock signal may be used as a timing reference signal for adjusting an operating rate or an input/output timing of the semiconductor device.
Since the clock signal may be used as the timing reference signal, an ideal clock signal may have the same slew rate and the same duty rate throughout the semiconductor device. Furthermore any skew or delay time difference may be eliminated. However, various signals, including the clock signal, may be transmitted through transmission lines such as metal lines and the like in the semiconductor device. In such a transmission process, the same signal may not be applied throughout the semiconductor device at the same timing because the signal may be delayed or distorted. When the clock signal is not uniformly applied throughout the semiconductor device, a timing margin of the semiconductor device may be reduced. The reduced timing margin may lead to an abnormal operation. Since the timing margin is important, equal distribution of the clock signal throughout the semiconductor device may be considered when designing the semiconductor device.
FIG. 1 illustrates an example of a single chip package (SCP) semiconductor device in which transmission lines may be arranged in an H-tree circuit network technique. In FIG. 1, the transmission lines may be arranged such that an externally applied clock signal may be uniformly distributed throughout the semiconductor device.
The SCP semiconductor device may have a single chip 10 within a package. A clock signal CLK may be uniformly distributed in all regions on the single chip 10. A transmission line (HL) arrangement illustrated in FIG. 1 is based on a signal distribution method known as an H-tree circuit network technique.
In the H-tree circuit network technique, a reference transmission line ML is arranged such that the clock signal CLK may be applied to a middle position of the chip 10. A first H transmission line HL1, may be coupled to the reference transmission line ML and transmit the clock signal CLK to the middle position of each of four regions into which the chip 10 is uniformly divided. First H transmission line HL1 may serve as a highest layer transmission line. For example, the reference transmission line ML may be coupled to the H transmission line HL1 and a center of H transmission line HL1. The H transmission line HL1 may have four end points. Each of the four end points of the H transmission line HL1 may be coupled to a corresponding middle position of each of the four regions of the chip 10.
Second H transmission lines HL2 may serve as lower layer transmission lines than the first H transmission line HL1. The middle of each second H transmission line HL2 may be coupled to a corresponding end of the first H transmission line HL1. For example, the middle of H transmission line HL2 may be coupled to the corresponding end of first H transmission line HL1. The second H transmission line HL2 may transmit the clock signal CLK to a middle position of each of four sub-divided regions of each of the four regions of the chip 10. A region where the clock signal CLK may be distributed in the chip 10 may be further sub-divided by third H transmission lines HL3 and fourth H transmission lines HL4 serving as lower layer transmission lines. For example, H transmission lines HL1, HL2, HL3 and HL4 may serve as first, second, third and fourth layer H transmission lines, respectively.
An input buffer 20 may accurately detect a signal level of the externally applied clock signal CLK, and may drive the clock signal CLK such that the clock signal CLK is accurately transmitted to the last H transmission line HL4 of the H-tree. The input buffer 20 may include a first buffer bf and a driving buffer drvbf. The first buffer bf may receive the externally applied clock signal CLK, and may detect the level of the clock signal CLK. The driving buffer drvbf may have high drive capability and may increase a swing width of the clock signal CLK output from the first buffer bf.
In FIG. 1, the fourth H transmission lines HL4, or the lowest layer should there be more than four layers of H transmission lines, may be coupled to various elements 11 implemented on the chip 10. Since the clock signals CLK applied to the elements 11 may be applied via the H transmission lines HL1-HL4, the signals may be applied via similar paths. Consequently, the clock signal CLK may be applied to each element 11 at the same timing and in the same phase throughout the chip 10.
In FIG. 1, H transmission line layers may include four layers, the first, second, third and fourth H transmission lines HL1, HL2, HL3 and HL4. However, it should be noted that the number of H transmission line layers may be decreased or increased.
FIG. 2 is a diagram illustrating a method for distributing a signal throughout a semiconductor device using a ladder type circuit network technique in the SCP semiconductor device.
The ladder type circuit network technique is a device using a phase interpolation that is disclosed in Korean Patent No. 10-0366629 (Yeong-don CHOI et al.) published on Dec. 17, 2002, the entire contents of which are incorporated herein by reference. In phase interpolation, a plurality of signals that has a small phase difference and is coupled via transmission lines may be combined to obtain one signal. For the sake of brevity, a more detailed description will be not be provided.
The ladder type circuit network technique shown in FIG. 2 may include an input buffer 21, two or more ladder transmission lines LL1 and LL2 extending side-by-side and a plurality of buffers b11-b2n. The buffers b11-b1n may be coupled in parallel between the adjacent ladder transmission lines LL1 and LL2. The input buffer 21 may operate in a similar or substantially similar manner as the input buffer 20. Thus, for the sake of brevity, the input buffer 21 will not be discussed in further detail. The plurality of buffers b11-b2n may have the same signal delay time.
A clock signal CLK applied to the first ladder transmission line LL1 through the input buffer 21 may be transmitted to the second ladder transmission line LL2 through the buffers b11-b1n provided between the first ladder transmission line LL1 and the second ladder transmission line LL2. The buffers b11-b1n may have the same signal delay time as one another. Therefore, time delay differences from a plurality of clock signals CLK applied to the second ladder transmission line LL2 through the buffers b11-b1n may have delay time differences due to distances through the first and second ladder transmission lines LL1 and LL2. Hence, the delay time difference between the clock signal CLK applied to the second ladder transmission line LL2 through the buffer b11 and the clock signal CLK applied to the second ladder transmission line LL2 through the buffer b1n may be small. Thus, the plurality of clock signals CLK applied to the second ladder transmission line LL2 may be phase-interpolated and merged into one clock signal CLK.
While only two rows of buffers and transmission lines are shown in FIG. 2, it should be understood that more than two rows may be used. When the ladder type circuit network technique is applied to the SCP semiconductor device, a plurality of ladder transmission lines of all regions on the chip may be arranged on the chip side-by-side, and a plurality of buffers may be provided between the adjacent ladder transmission lines. The plurality of ladder transmission lines LL1-LL2 may be arranged in a zigzag form or a vortex form. It should be noted that lines may be arranged in any form throughout the chip such that they do not overlap.
The conventional signal distribution methods in the SCP semiconductor device have been described with reference to FIGS. 1 and 2. However, highly integrated and multi-functional semiconductor devices may be required for miniaturized and multi-functional electronic products. A multi-chip package (MCP) semiconductor device in which a plurality of chips is packaged into a single semiconductor device has been introduced. The MCP semiconductor device may be a single layer type MCP semiconductor device or a multi-layer type MCP semiconductor device. The single layer type MCP semiconductor device is a semiconductor device in which a plurality of chips may be arranged side-by-side and packaged. The multi-layer type MCP semiconductor device (e.g., a stacked semiconductor device) is a semiconductor device in which a plurality of chips may be stacked and packaged.
FIG. 3 illustrates a signal distribution path in a conventional stacked semiconductor device.
In contrast to the SCP semiconductor device and the single layer type MCP semiconductor device, the stacked semiconductor device may have a three dimensional structure including a plurality of stacked chips Cp1-Cp5, as shown in FIG. 3. Similar to the SCP semiconductor device and the MCP semiconductor device, a clock signal may be distributed throughout the semiconductor device.
The stacked semiconductor device shown in FIG. 3 has the plurality of stacked chips Cp1-Cp5 oriented in a stacked vertical fashion. A main signal line MLM may pass through the plurality of stacked chips Cp1-Cp5, so that a signal is distributed to each of the plurality of stacked chips Cp1-Cp5. A host chip Host, serving as an internal or external device of the stacked semiconductor device, may have a reference transmission line ML and an input buffer 120. Additionally, the host chip Host may supply a clock signal CLK to the stacked semiconductor device. The input buffer 120 may be similar to the input buffers 20 and 21 of FIGS. 1 and 2, respectively. The input buffer 120 may drive and output the clock signal CLK such that the clock signal CLK is smoothly distributed to the plurality of chips Cp1-Cp5. An example in which the host chip Host is additionally provided is illustrated in FIG. 3. However, it should be understood that the host chip Host may not need to be additionally provided when one of the plurality of stacked chips Cp1-Cp5 is configured to have the reference transmission line ML and the input buffer 120 in order to receive an external clock signal CLK.
The plurality of chips Cp1-Cp5 may uniformly transmit the clock signal CLK to all regions on the plurality of stacked chips Cp1-Cp5 using the H-tree circuit network technique or the ladder type circuit network technique. As shown in FIG. 3, the main signal line MLM is arranged in a node NodeA such that the clock signal CLK can be transmitted from the middle of the plurality of chips Cp1-Cp5 as in FIG. 1.
The plurality of stacked chips Cp1-Cp5 may be the same as one another or may be different from one another. When the plurality of stacked chips Cp1-Cp5 is the same as one another, a timing margin for transmitting an inter-chip signal or a signal level may be easily set since chip characteristics may be similar. However, when the plurality of stacked chips Cp1-Cp5 of the stacked semiconductor device is different from one another, it is relatively difficult to set a timing margin for transmitting an inter-chip signal or a signal level since characteristics may differ according to a difference in a chip structure, a manufacturing process, or the like.
In order to distribute a signal throughout the semiconductor device in the above-described stacked semiconductor device, it is important to uniformly distribute the clock signal CLK to the plurality of stacked chips Cp1-Cp5. If the clock signal CLK to be applied to the plurality of stacked chips Cp1-Cp5 is not uniformly distributed, the clock signal CLK may be different among the plurality of stacked chips Cp1-Cp5 even when the clock signal CLK is uniformly distributed from the chips Cp1-Cp5.
However, as shown in FIG. 3, the conventional stacked semiconductor device is configured to smoothly distribute a signal using the H-tree circuit network technique or the ladder type circuit network technique for an internal signal distribution of each of the plurality of stacked chips Cp1-Cp5. The conventional stacked semiconductor device may use a simple signal transmission technique through the main signal line MLM for a signal distribution to the plurality of stacked chips Cp1-Cp5. However, when one of the plurality of stacked chips Cp1-Cp5 is far away from the host chip Host, the far away chip has a larger delay than another of the plurality of stacked chips Cp1-Cp5 that is closer to the host chip Host. Therefore, there is a high possibility that the applied clock signal may be distorted. That is, the signal applied to the plurality of stacked chips Cp1-Cp5 may be skewed.